Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
Conventionally, upon patterning a polysilicon gate electrode, the doping of the polysilicon is performed concurrently with the formation of the source/drains on opposing sides of the gate electrode in the semiconductor body. Typically, heavy doping at this stage is desirable in order to avoid poly depletion and thus keep oxide thickness (Tox) as small as possible. However, too much doping in the source/drain regions can lead to overrun of the extension regions, and lead undesirably to punchthrough and/or leakage.
The necessity to control Short Channel Effects (SCE) requires the complete suppression of dopant diffusion in order to control the lateral and vertical depth and the abruptness of the junction profile. It is known that junctions formed by Solid Phase Epitaxial Regrowth (SPER) of a doped amorphous region allow for meta-stable high activation level and perfectly abrupt profiles. The excellent abruptness of SPER junction results from a poor activation level in the crystalline Si below the amorphous region. Despite the excellent vertical junction profile, several integration issues rise from the lateral amorphisation and from the End of Range (EOR) defects. A strong dependence is often observed of the lateral amorphous region profile near the gate on the implantations used in the prior art. Unless optimized this leads to poor doping active concentration under the gate that significantly increases the overlap resistance. Through a SPER extension process, species combinations of Ge, BF2 and B for PMOS, and As for NMOS have been characterized for transistor performance. Under the correct conditions, the transistor performance can be recovered. An optimised SPER junction can preserve the oxide integrity and avoid the degradation of the poly.
Accordingly, there is a need for improved transistor fabrication methods for processing by which the benefits of decoupling the conventional tradeoff between oxide integrity and degradation of the poly can be achieved while avoiding or mitigating the problems encountered in conventional techniques.